Defect and temperature dependence of tunneling in InGaAs/GaAsSb heterojunctions with varying band alignments

Recently, tunnel field effect transistors (TFET) based on heterostructures with type-II and type-III band alignment have been proposed as a means of obtaining switching at room temperature with subthreshold slopes below the thermal limit of 60 mV/decade, and without sacrificing drive current [1,2] While early computational efforts have delivered promising results, experimental work has not seen switching steeper than the thermal limit [3]. Since computational work to date has assumed defect-free structures [1,2], it is important to study the types of materials defects and properties that are present in these structures, and learn how they affect device performance. Furthermore, most published heterojuction TFET results exhibit a pronounced temperature dependence in which subthreshold slope increases in steepness considerably as temperature is cooled, although never beyond the thermal limit [3-5]. Such a temperature dependence is unexpected since the nature of interband tunneling leads to a cut-off of the thermal band-tails. It has been proposed that this temperature dependence may be a parasitic effect related to trap-assisted tunneling and generation into the conduction band via gate oxide interface trap states [4].