DocumentCode :
3697959
Title :
A 0.68V 0.68mW 2.4GHz PLL for ultra-low power RF systems
Author :
Arun Paidimarri;Nathan Ickes;Anantha P. Chandrakasan
Author_Institution :
EECS, Massachusetts Institute of Technology, Cambridge, USA
fYear :
2015
fDate :
5/1/2015 12:00:00 AM
Firstpage :
397
Lastpage :
400
Abstract :
A 2.4GHz PLL consuming 0.68mW has been implemented in 65nm LPCMOS for use in ultra-low power Bluetooth Low Energy (BLE) applications. VCO, charge pump and dynamic flip-flop design optimization allow low voltage operation at 0.68V, bringing down dynamic power. The integer-N PLL covers all BLE channels and has a phase noise of −110dBc/Hz at 1MHz offset. To extend operation to extremely low duty cycles, extensive power gating is applied to bring the leakage power down to 170pW.
Keywords :
"Phase locked loops","Voltage-controlled oscillators","Charge pumps","Phase noise","Radio frequency","Low voltage","Power demand"
Publisher :
ieee
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2015 IEEE
Type :
conf
DOI :
10.1109/RFIC.2015.7337789
Filename :
7337789
Link To Document :
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