DocumentCode :
3698498
Title :
A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor
Author :
Haruki Mori;T. Nakagawa;Y. Kitahara;Y. Kawamoto;K. Takagi;S. Yoshimoto;S. Izumi;K. Nii;H. Kawaguchi;M. Yoshimoto
Author_Institution :
Kobe University, Kobe, Japan
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bitcells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip can operate at a supply voltage of 0.46 V and an access time of 140 ns. The energy minimum point is a supply voltage of 0.54 V and an access time of 55 ns (= 18.2 MHz), at which 298 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved with the help of the majority logic; these factor are 87% and 52% smaller than those in a 28-nm FD-SOI 6T SRAM.
Keywords :
"Transistors","SRAM cells","Yttrium","Logic circuits","Logic gates","Semiconductor device measurement"
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2015 IEEE
Type :
conf
DOI :
10.1109/CICC.2015.7338360
Filename :
7338360
Link To Document :
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