DocumentCode :
3698504
Title :
A soft-error hardened process portable embedded microprocessor
Author :
Vinay Vashishtha;Lawrence T. Clark;Srivatsan Chellappa;Anudeep R. Gogulamudi;Aditya Gujja;Chad Farnsworth
Author_Institution :
Arizona State University, Tempe, AZ, USA
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
An embedded microprocessor core designed to have high soft-error immunity is presented. The design achieves hardness via architectural, micro-architectural, and circuit techniques. The basis of the machine is a dual-redundant speculative pipeline that detects mismatches at their commission to architectural state. Added instructions allow software controlled recovery and restart of upset instructions. Key architectural state is stored in triple-mode redundant, self-correcting logic. Special automated place and route flows afford robustness against multiple node charge collection. Full clock gating allows low power, while redundant clocks mitigate clock upset induced errors. Register file based caches allow near-threshold low voltage operation. The design is implemented on a commercial 90-nm bulk CMOS process. Silicon results, including error correction examples, are presented.
Keywords :
"Clocks","Radio frequency","Registers","Tunneling magnetoresistance","Silicon","Pipelines","Standards"
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2015 IEEE
Type :
conf
DOI :
10.1109/CICC.2015.7338366
Filename :
7338366
Link To Document :
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