A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology

This paper presents a 40Gbps SerDes transceiver consuming only 190mW power. The transmitter employs serializing time window search technique and 2-tap pre-emphasis. The receiver implements power-efficient front-end circuits including current-integrating FFE and cascaded dynamic comparators. The CDR employs a bang-bang phase detector, and the integral path and proportional path are separated. Fabricated in 65nm technology, the receiver BER is below 1e-12 under 15dB channel loss. The total jitter of transmitter 40Gbps eye diagram is 6.7ps for 1e-12 BER. The phase noise of recovered clock is −122dBc/Hz at 1MHz and recovered data peak-peak jitter is 26ps.