Fast statistical analysis of rare circuit failure events via Bayesian scaled-sigma sampling for high-dimensional variation space

Accurately estimating the rare failure events of nanoscale ICs in a high-dimensional variation space is extremely challenging. In this paper, we propose a novel Bayesian scaled-sigma sampling (BSSS) technique to address this technical challenge. BSSS can be considered as an extension of the traditional scaled-sigma sampling (SSS) approach. The key idea is to explore the “similarity” between different SSS models fitted at different design stages and encode it as our prior knowledge. Bayesian model fusion is then adopted to fit the SSS model with consideration of the prior knowledge. A sense amplifier example designed in a 45 nm CMOS process is used to demonstrate the efficacy of BSSS. Experimental results demonstrate that BSSS achieves superior accuracy over the conventional SSS and minimum-norm importance sampling approaches when a few hundred random variables are used to model process variations.