DocumentCode
3698556
Title
Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS
Author
Minki Cho;Carlos Tokunaga;Muhammad M. Khellah;James W. Tschanz;Vivek De
Author_Institution
Circuit Research Lab, Intel labs, Hillsboro, OR
fYear
2015
Firstpage
1
Lastpage
4
Abstract
Aging-aware Adaptive Voltage Scaling (AVS) can eliminate conventional flat voltage guard band typically added to intrinsic chip VCC to account for transistor aging, therefore reducing power consumption throughout the lifetime of the chip. Aging-aware AVS applied to a Tunable Replica Circuit (TRC) built in a 22nm test chip demonstrates a measured power reduction of a maximum of ∼7% at beginning of life and a minimum of ∼2% at end of life.
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2015 IEEE
Type
conf
DOI
10.1109/CICC.2015.7338419
Filename
7338419
Link To Document