DocumentCode :
3698562
Title :
An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier
Author :
Bongjin Kim;Hoonki Kim;Chris H. Kim
Author_Institution :
University of Minnesota, Minneapolis, MN 55455 USA
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
An 8bit two-step time-to-digital converter (TDC) with a novel digital switched ring-oscillator based time amplifier (TA) is demonstrated in 65nm CMOS. The proposed TA achieves a predictable and programmable gain without requiring any calibration. The implemented 8bit two-step TDC with a 16x TA gain achieves a time resolution of 2.6ps at 80MS/s conversion rate while consuming 2mW. The measured DNL and INL are 1.84LSB and 2.36LSB, respectively. The TDC area is 0.07mm2.
Keywords :
"Delay lines","Switching circuits","Delays","Logic gates","Switches","CMOS integrated circuits","Calibration"
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2015 IEEE
Type :
conf
DOI :
10.1109/CICC.2015.7338425
Filename :
7338425
Link To Document :
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