A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS

A 0.6 V low energy 64 kb SRAM-based PUF macro protected with a multi-bit error correcting circuit is fabricated in a 28 nm LP-CMOS process. The static noise margin difference (ΔSNM) is proposed as a design-time cell asymmetry metric for characterizing bitcell PUF response reproducibility. The ΔSNM is then used in conjunction with a Pelgrom´s model based design methodology to compare a set of eight 6T SRAM bitcells designed to operate over a 0.6 V to 1.0 V voltage range. Majority voting and data integrity masking is used to reduce the error correction parity-bit overhead by 65% to yield 100% reproducible PUF responses. Finally, measurement results over a set of five test chips show an average active access energy of 0.045 fJ/bit-cycle.