Open loop and closed loop solution for clock domain crossing faults

Modern digital systems become more complex with increasing multi-clocking techniques for better performance. Multiple asynchronous clock domains have been using for different I/O interface in today´s modern system on chip (SoC). Each system needs to communicate with one or other system/peripherals continuously. These multiple asynchronous clock domains are facing meta-stability, data losses and other clock domain crossing (CDC) issues. CDC is an important issue in all today´s SoC. To overcome the clock domain crossing(CDC) issues such as meta-stability and data losses, basic two flip-flop synchronizer has been designed whose performance is depends on pulse width of transmitting signal across the different clock domains, which has to be greater than 1.5X the receiver domain clock width. In this paper a short pulse synchronizer has been designed and demonstrated for variable pulse width, whose performance is independent on pulse width of the signal which transmits across the domains.