A study on high-? gate stack for MOS-FET

At submicron range below 45 nm technology for MOS transistors, leakage power dissipation is a critical concern other than dynamic and short circuit power dissipation. This happens due to the effect of low level dielectric property of Silicon dioxide (SiO2) gate insulator. It has been observed that the leakage power dissipation is reduced further to a large extent using high-κ dielectric. In this paper, we will study the nature of high-κ dielectric material in lower submicron NMOS Technology using “MINIMOS-NT Global TCAD” simulation software. The role of leakage current for a few high-k gate materials in singular and in stacks will be determined from the transfer characteristics of a MOS transistor. The study has been extended to Gate Stack dielectric materials for NMOS. Some interesting results have been presented here, using some high-k dielectric materials.