Low power and high testable Finite State Machine synthesis

As the density of the VLSI chip increases, the testing and power consumption are becoming major concerns for its use in various applications. To reduce the expense of the VLSI chip design especially for the testability and low power consumption, the optimization has to be considered near the beginning stage of the design such as logic synthesis level. Power and testability issues of FSM (Finite State Machine) during synthesis are considered in this paper. For the FSM circuits at the logic synthesis level synthesis is done for the reduction of both power consumption and increase in testability. To do so during synthesis both the power and fault coverage which is the measure of testability are taken together in the cost function of GA (Genetic Algorithm) and are optimized. Reduction of power dissipation may leads to decrease in fault coverage. So, there is a trade-off between power and fault coverage. This trade-off analysis has been performed and finally after synthesis a circuit that has optimum power and highest fault coverage is obtained.