A 0.8/0.9-V 5.4-GHz phase-locked loop with inductance coupled VCO in 0.18-?m CMOS

Implemented in a standard 0.18-μm CMOS process, a 0.8/0.9-V 5.4-GHz low-power phase-locked loop (PLL) is presented. In the prescaler, the first-stage divide-by-2 prescaler is structed with LC-type VCO by inductance coupled to perform frequency division. The next-stage divide-by-2 divider uses the conventional D-type filpflop with optimizing the threshold voltage to lower the operating voltage. As the building blocks are optimized for low-voltage and low-power operations, the fabricated 5.4-GHz PLL consumes a dc power of 4.8 mW from a 0.8/0.9-V and phase noise of -109.6 dBc/Hz at 1-MHz offset.