Low-power design towards implantable neural signal processor- energy efficiency analysis for near-threshold voltage circuits design

In this paper, we review state-of-the-art low-voltage fault-tolerable logic techniques that are promising for medical implants. The paper also proposes a method to get the efficiency comparison of computational time delay, power consumption, energy efficiency and progress variation of logic gates such as static, transmission gate, DCVSL, dynamic and pesudo in different temperature, time and variations so that the researchers can have a design reference for ultra low-power digital blocks of the implantable systems.