A formal design methodology for synthesizing a clock signal with an arbitrary duty cycle of M/N

Nowadays, the emerging research topic on synthesizing logic functions with chemical reaction networks (CRNs) have drawn intensive attentions from both academia and industry. By making use of its advantages in power, spontaneity, robustness, and parallelization, a lot of amazing applications of this research topic have been proposed and therefore give this field a promising future. However, in order to properly synthesize sequential logics with CRNs, the difficulties in construct a clock signal with an arbitrary duty cycle turns out to be a bottleneck. To this end, this paper devotes itself in constructing a formal design methodology, which can conveniently generate clock signals with any duty cycle of M/N. In order to achieve this goal, we put our efforts in steps. First, clock signal with duty cycle of 1/N with N ≥ 3 is introduced. Then, the case of 1/2 duty cycle is taken care of. Finally, clock signal with duty cycle of M/N is constructed in a nice manner with the aid of circle map representation.