• DocumentCode
    3703709
  • Title

    Parallel block-layered nonbinary QC-LDPC decoding on GPU

  • Author

    Huyen Thi Pham;Sabooh Ajaz;Hanho Lee

  • Author_Institution
    Department of Information and Communication Engineering, Inha University, Incheon, 402-751, Korea
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    This paper presents an efficient implementation of a parallel block-layered nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) decoder on a graphics processing unit (GPU) to achieve significant improvements in both flexibility and scalability. An efficient block-layered scheme and a data structure suitable for parallel computing are proposed to perform decoding on the GPU. The scheme is applied to a min-max decoding algorithm that exploits the inherent massive parallelization capabilities of NB-QC-LDPC decoder. The results of the proposed approach demonstrate that the layered scheme can be efficiently implemented in a GPU device. Moreover, experimental results show that the proposed GPU-based block-layered NB-QC-LDPC decoder provides a faster decoding runtime compare to CPU-based implementation and obtains a coding gain under a low 10-10 BER and low 10-7 FER.
  • Keywords
    "Graphics processing units","Decoding","Algorithm design and analysis","Iterative decoding","Kernel","Manganese"
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Systems (SiPS), 2015 IEEE Workshop on
  • Type

    conf

  • DOI
    10.1109/SiPS.2015.7345000
  • Filename
    7345000