An X-band 9.75/10.6 GHz low-power phase-locked loop using 0.18-?m CMOS technology

An X-band 9.75/10.6 GHz fully-integrated low-power consumption phase-locked loop (PLL) is designed and fabricated on standard 0.18-μm CMOS process. Through the band control circuit of the voltage control oscillator (VCO) and mode control of the 7-bit divide-by-128~255 multi-modulus frequency divider (MMD), the PLL output frequency of 9.75 GHz and 10.6 GHz is synthesized successfully with a reference source of 12.5 MHz. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) based 2/3 cell divider, the PLL achieves low power consumption of 24 mW with good phase noise. The measured closed loop phase noise of the PLL at a frequency offset of 10 MHz is -116.24 dBc/Hz and -122.64 dBc/Hz with center of 9.75 GHz and 10.6 GHz, respectively.