A WLAN RF CMOS power amplifier with power detector, high harmonic suppression, and temperature compensation

A fully integrated 2.45 GHz power amplifier with a power detector, harmonic suppression techniques, and temperature compensation circuits is implemented through 55-nm CMOS technology. Using bias-control variable resistors, the proposed power detector has wide dynamic range and low linear error. Utilizing the harmonic suppression techniques; the proposed power amplifier is able to deliver signals without disturbing adjacent circuits. With the temperature compensation circuit, the proposed power amplifier can provide consistent performances at different temperatures. The measured dynamic range and linear error of the power detector are 16 dB and <;0.8 dB at 2.45 GHz, respectively. The power amplifier has second and third harmonic suppression of 35.6 and 43.8 dBc when the output power of the power amplifier is 17.6 dBm. These techniques are essential for high-yield mass production of power amplifier products.