A novel leakage reduction DOIND approach for nanoscale domino logic circuits

Dynamic CMOS logic circuits are used in modern VLSI circuits because of its high system performance and its performance is high due to higher speed over static CMOS circuit. However dynamic logic circuit has less noise immunity and increased leakage power dissipation. Increase in leakage current combine with reduced noise margin results in performance degradation of dynamic circuits. In this paper DOIND logic approach is proposed for domino logic which reduces the leakage current with minimum delay penalty. Simulation is performed at 70 nm technology node for a domino logic and DOIND logic buffer using tanner EDA tool. Simulation results shows that proposed DOIND approach decreases the leakage current 93.3%, static power 93.3% and static energy 86.66% at supply voltage 1.15V. Proposed circuit also improves dynamic power 60.78%, dynamic energy delay product (EDP) 62.18% and dynamic power delay product (PDP) 62.07% at 1.15V supply voltage.