Characterizing impacts of multi-Vt routers on power and reliability of Network-on-Chip

Prolong advancements in technology scaling over the past few years eventually leads to the development of multi core processors. Network On Chip architecture is a promising paradigm to attain higher network density in high performance multi core computing systems. In today´s scenario, with the growing number of transistors, power density is becoming prominent issue in the network design. Therefore, the researchers are constantly focusing on accurate estimation of system power which ultimately leads to system reliability enhancement. In this paper, an experimental setup is formulated to analyze the working of multi-Vt NoC routers and their impacts on system power. Different life time distribution schemes are adopted for accurate reliability estimation. We have done the power analysis on the basis of multi-threshold voltage cells which is a low power technique i.e. low Vt (LVT), normal Vt (NVT) and high Vt (HVT) routers and reliability analysis by using two life time distributions i.e. lognormal and weibull and have compared their results. We have also done the comparative analysis with the previous integrated power model on the basis of reliability, transistor performance, architectural and technological parameters. The reliability results by weibull distribution for LVT routers shows 35% degradation as compared to HVT routers and for lognormal the difference is 56%.