Two phase sinusoidal power clocked quasi-static adiabatic logic families

The paper presents the comprehensive analysis and evaluation of static adiabatic logic circuits operated by two phase sinusoidal clock signals. The static adiabatic logic has an advantage in the form of reduction in switching energy while comparing with the dynamic adiabatic logic. This advantage is realized due to the fact that the discharging operation at a node happens only when the input signal transition demands a change in the state of the output. Or in other words, if the next input state happens to be the same as the present state, the charged output nodal state remains the same, without undergoing any recovery phase. The analysis of the static adiabatic logic is done using a carry look ahead adder (CLA) implemented by static adiabatic families, namely, QSERL, CEPAL, ASL and QSECRL and comparing them against the static CMOS counterpart. The performance of each of the circuit is studied in terms of the frequency and power clock voltage range of operation. The simulations show that the 8-bit CLA static adiabatic adder realizes energy reduction from 45% to 83% over a frequency range of 100 KHz to 500MHz operation against the static CMOS implementation. The analyses were carried out using SPICE EDA tools using 180 nm technology library from TSMC.