Title :
IBIS-AMI modelling of high-speed memory interfaces
Author :
John Yan;Arash Zargaran-Yazd
Author_Institution :
Rambus Inc., Sunnyvale, CA, USA
Abstract :
This paper presents techniques to accelerate the exploration of advanced memory links through IBIS-AMI modelling of the transmitter and receiver. The results show over 1000× CPU time speed improvement compared to full transistor level SPICE simulations while providing a fair representation of the interface performance. To demonstrate the versatility the IBIS-AMI for memory interfaces, data transmission at 2.4 Gbps and 6.4 Gbps, over the same multidrop channel with different equalization features, are presented.
Keywords :
"Integrated circuit modeling","Decision feedback equalizers","Transceivers","Table lookup","Acceleration","Receivers","Transistors"
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2015 IEEE 24th
Print_ISBN :
978-1-5090-0038-8
DOI :
10.1109/EPEPS.2015.7347132
