Novel de-embedding method with Look-Up Table for characterization of interconnects

A new de-embedding technique is introduced in this paper with pre-established Look-Up Table (LUT) for accurate characterization of high speed interconnects, particularly for printed circuit board (PCB). The method de-embeds the test fixture effects from the measurement or/and simulation results. It improves the accuracy and reduces the PCB layout area comparing to one line method. It reduces the PCB layout area and improves the measurement efficiency comparing to two line method.