• DocumentCode
    3705465
  • Title

    Performace modeling and optimization for on-chip interconnects in memory arrays

  • Author

    Javaneh Mohseni;Chenyun Pan;Azad Naeemi

  • Author_Institution
    School of Electrical and Computer Engineering, Georgia Institute of Technology, 791, Atlantic Drive, NW, Atlanta, 30332-0269, USA
  • fYear
    2015
  • Firstpage
    149
  • Lastpage
    152
  • Abstract
    Performance modeling and optimization for on-chip interconnects in DRAM arrays are presented at various technology generations. Multiple interconnect design schemes and novel interconnect technology options are investigated to minimize the overall delay and energy-delay product.
  • Keywords
    "Delays","Integrated circuit interconnections","Copper","Wires","Integrated circuit modeling","Decoding","Wiring"
  • Publisher
    ieee
  • Conference_Titel
    Electrical Performance of Electronic Packaging and Systems (EPEPS), 2015 IEEE 24th
  • Print_ISBN
    978-1-5090-0038-8
  • Type

    conf

  • DOI
    10.1109/EPEPS.2015.7347150
  • Filename
    7347150
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3705465