Analysis and system optimization of high performance clocking for modern mobile platforms

Modern mobile platforms contain mainly active components in a small area with stringent power and cost targets. An integrated clock is needed for PLLs, component internal functions as well as transferring data among them. Due to the small mobile form factors, the noise coupling from power/ground and signals to the integrated clock circuitry becomes more evident impacting clock performance significantly. A method of signal and power integrity analysis and system optimization is proposed to design clocks in System-on-Chip (SoC), package and platform of mobile products such as wearables, phones and tablets. The measured results from high volume mobile systems show 30% clock jitter reduction from generation to generation using the frequency domain analysis and system optimization.