Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs

This paper reports the reuse of smaller optimized FFT (Fast Fourier Transform) blocks for the realization of larger power efficient radix-2 FFTs. The smaller FFT blocks use Constant Matrix Multiplication (CMM) method along its stages that are implemented with Carry Save Adders (CSA). The use of CMM at gate level enables the replacement of the multiplication operations by addition/subtractions and shifts for each stage of the real and imaginary parts of the FFT butterflies. The larger FFT is obtained through the composition of the optimized smaller FFT modules. Through a control unit, the partial decomposition of coefficients allows the computation of all coefficients necessary for the larger FFTs. The use of pipeline into the stages of the FFT enabled gains in both power and performance when compared with the previous non-pipelined solution. Moreover, the results showed that, when using pipeline, our solution is more delay and power efficient when compared with prominent works from the literature.