AES IP for hybrid cryptosystem RSA-AES

AES (Advanced Encryption Standard) is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting data. In this paper, we present three hardware architectures for AES, namely Serial/Serial, Parallel /Serial and Parallel/Pipelined. These architectures can be used as IP (Intellectual Property) cores in hybrid cryptosystem RSA-AES implemented on an FPGA PSoC (Programmable System on Chip). The highlights of our work are: implementing S-Box memories of AES SubBytes transformation on Slices of FPGA which reduces the hardware resources and using the Xtime() functions in the implementation of AES MixColumns transformation which accelerate its execution time. Such architectures cater to different applications and offer good tradeoffs between performances and occupied areas.