32k Channels readout IC for single photon counting detectors with 75 ?m pitch, ENC of 123 e? rms, 9 e? rms offset spread and 2% rms gain spread

The paper presents a readout integrated circuit called UFXC32k designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The UFXC32k integrated circuit designed in CMOS 130 nm process, contains about 50 million transistors in the area of 9.64 mm × 20.15 mm. The core of the IC is the matrix of 128 × 256 square shaped pixels of 75 μm pitch. Each pixel contains a charge sensitive amplifier, a shaper, a discriminator, correction circuits and two 14-bit counters. The data is read out via 8 Low Voltage Differential Signaling (LVDS) outputs. The UFXC32k chip is bump-bonded to a pixel silicon sensor and fully characterized in X-ray radiation. The measured equivalent noise charge is equal to 123 e^- rms (for the peaking time of 40 ns) and each pixel dissipates 26 μW. Thanks to the use of multilevel offset correction, an effective offset spread calculated to the input is only 9 e^- rms with the gain spread of 2 %.