• DocumentCode
    3706357
  • Title

    Analysis of delay time in subthreshold CMOS circuits operating at ultra-low supply voltage

  • Author

    Seung-Min Jung;Takuya Saraya;Toshiro Hiramoto

  • Author_Institution
    Institute of Industrial Science, The University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan
  • fYear
    2014
  • fDate
    6/1/2014 12:00:00 AM
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    The speed of subthreshold CMOS circuits is analyzed by circuit simulation. In particular, the dependences on drain-induced barrier lowering (DIBL) and load capacitance are evaluated and compared with CMOS circuits operating at normal supply voltage (Vdd). It is found that the speed of subthreshold circuits is much more degraded by DIBL than that of normal circuits because the peak transient drain current is more lowered by DIBL. On the other hand, it is also found that the effect of DIBL does not depend on load capacitance.
  • Keywords
    "Delays","Trajectory","CMOS integrated circuits","Capacitance","Degradation","Circuit simulation","Transient analysis"
  • Publisher
    ieee
  • Conference_Titel
    Silicon Nanoelectronics Workshop (SNW), 2014 IEEE
  • Print_ISBN
    978-1-4799-5676-0
  • Type

    conf

  • DOI
    10.1109/SNW.2014.7348594
  • Filename
    7348594
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3706357