A low-power 490 mpixels/s hardware accelerator for pyramidal decomposition of images

This paper introduces a pyramidal decomposition system suitable for high frame rate and real-time applications. The presented system´s architecture omits the image transpose block used in standard separable filters, and implements internal downsampling to reduce number of computations. The decomposition is implemented in form of a field programmable gate array (FPGA) hardware accelerator and the presented results show the low resource utilization of the design. The internal downsampling reduces the power consumption by an order of magnitude compared to state-of-the-art, which makes this accelerator an excellent addition to co-processors on mobile platforms.