Design of high speed CCD data acquisition system based on FPGA and USB3.0

The high-speed area array CCD (Charge Coupled Devices) signal acquisition system based on FPGA and USB3.0 interface is introduced in this paper. The hardware components of the system, the firmware of the USB interface control chip and an interface module in FPGA to fit the GPIF II are discussed. A PC application is also developed based on MFC with Microsoft VC++. The testing results indicate that the designed system works reliably, which can acquire and save the CCD data at a high speed with a good performance.