Title :
Impact of size variation in junctionless vs junction planar SOI n-MOSFET transistor
Author :
A. R. N. Huda;M. K. Md Arshad;Noraini Othman;C. H. Voon;R. M. Ayub;Subash C. B. Gopinath;K. L. Foo;A. R. Ruslinda;U. Hashim;H. Cheun Lee;P. Y. P. Adelyn;S. M. Kahar
Author_Institution :
Institute of Nano Electronic Engineering, Universiti Malaysia Perlis, Kangar, Perlis, Malaysia
Abstract :
In this paper, the effect of silicon body thickness (TSi) and silicon body width (WSi) variation on DC characteristics in 100 nm gate length silicon-on-insulator (SOI) junctionless (JL) and junction transistors has been investigated by using numerical simulations. The digital figure-of-merits characteristics such as threshold voltage (VTH), on-current, subthreshold voltage, and drain-induced-barrier-lowering are the main parameters that have been investigated. Based on the simulations, the JT device is less sensitive to variation of TSi and WSi compared to JLT.
Keywords :
"Transistors","Silicon","Logic gates","Threshold voltage","Doping","Junctions","Numerical models"
Conference_Titel :
Micro and Nanoelectronics (RSM), 2015 IEEE Regional Symposium on
DOI :
10.1109/RSM.2015.7354983
