On limit cycles suppression in DC-DC Buck converters

This paper focuses on the analysis of limit cycles that appear on the output voltage of a DC-DC Buck converter. Typically, the output filter of the converter is designed in open-loop, considering the maximum allowable values for the output voltage and inductor current ripples. When closing the loop, the converter may exhibit unwanted periodic oscillations in steady state caused by the nonlinearities in the system. The amplitudes of these oscillations are hard to predict. This paper summarizes the conditions that should be taken into account when designing the closed loop converter. These conditions are used furthermore for tuning the PID parameters for a DC-DC Buck converter under input and load step scenarios. The tuning of the PID takes into consideration transient performances such as overshoot and settling time for specified test cases but also the conditions needed for removing the limit cycles from the output voltage.