Flexible high performance architecture for boundary scan execution hardware

IEEE 1149.1 boundary scan has become very popular since its introduction in the 1990s. It is now used routinely in defense and aerospace testing, and has become commonplace in new TPSes. But mil/aero quality requirements demand functional test as well. This means that boundary scan tests and functional tests must coexist in this environment. Boundary scan test requires access to the same UUT I/O signals as functional test. This is because many boundary scan tests, such as interconnect test, require control and observation of these signals to obtain full fault coverage. Functional test requires high-performance dynamic channels on the UUT I/O signals. The boundary scan requirements are less demanding. This paper proposes the use of configurable test hardware to address both requirements. This is technically achievable now that test systems can make use of FPGAs that can be efficiently reconfigured at run time. This paper proposes a boundary scan test architecture that can be combined with an existing functional test architecture in such a system. The boundary scan hardware architecture would be based on a specially designed processor optimized for boundary scan which would support up to 8 TAP ports. All available pins not used for TAP ports could be used for parallel I/O signals up to the constraints imposed by the limitations of the FPGA and fixturing. The custom processor could include throughput enhancing features such as pipelined double buffered DMA data transfer. With proper design, such a processor could run continuously as long as it was connected to a host computer that was fast enough to keep it supplied with data. Such a custom processor should be able to closely approach the device limited test time in throughput-critical situations, such as flash programming. It should be possible to straightforwardly control such hardware using a general purpose boundary scan runtime software library, which would present its client with an API that is conceptually similar to existing boundary scan languages like SVF and STAPL.