Reducing the cost of test for high-speed serial buses with COTS FPGA technology

Technology is trending towards more data, faster rates, smaller size, and less power. Better performance with a reduced footprint is hard to accomplish, but about 10 years ago, engineers solved this challenge for data movement by moving to a different digital communication paradigm. Instead of the traditional parallel buses that transmit clock and data separately, high-speed serial technology emerged that allows transmission of encoded data without the need for a separate clock signal. This has allowed industry to break the 1-2 GHz practical limit inherent to parallel busses and reach speeds over 50 GHz.