DocumentCode
3712324
Title
Logic simplification by minterm complement for error tolerant application
Author
Hideyuki Ichihara;Tomoya Inaoka;Tsuyoshi Iwagaki;Tomoo Inoue
Author_Institution
Graduate School of Information Sciences, Hiroshima City University, 3-4-1, Ozuka-higashi, Asaminami, Hiroshima 7313194 Japan
fYear
2015
Firstpage
94
Lastpage
100
Abstract
Error tolerant applications can tolerate specific errors, whose frequency and/or severity are within certain limits. This error tolerability is greatly instrumental in simplifying logic circuits for such applications. In this paper, we propose a logic simplification method for error tolerant application. Owing to error tolerance, we have an opportunity to complement several minterms of a given logic function within a threshold; if appropriate minterms are selected to be complemented, the given function can be greatly simplified. To select such minterms, we focus on two transformations, expansion and reduction, of prime implicants of the given logic function, and discuss the effect of the transformations on logic simplification. The proposed algorithm utilizing such transformations can efficiently find effective minterm complement. Experimental results show that, compared with a previous method, which employs only expansion of prime implications, the proposed algorithm can produce smaller logic circuits with reasonable computational effort.
Keywords
"Logic functions","Error analysis","Circuit faults","Combinational circuits","Algorithm design and analysis","Cities and towns"
Publisher
ieee
Conference_Titel
Computer Design (ICCD), 2015 33rd IEEE International Conference on
Type
conf
DOI
10.1109/ICCD.2015.7357089
Filename
7357089
Link To Document