DocumentCode
3712373
Title
Chameleon: Adaptive energy-efficient heterogeneous network-on-chip
Author
Ji Wu;Dezun Dong;Xiangke Liao;Li Wang
Author_Institution
National Laboratory for Parallel and Distributed Processing, School of Computer National University of Defense Technology, Changsha, China
fYear
2015
Firstpage
419
Lastpage
422
Abstract
Multi-NoC (multiple network-on-chip) has demonstrated its advantages in power gating for reducing leakage power. This work presents Chameleon, a novel heterogeneous Multi-NoC design. Chameleon employs a fine-grained power gating algorithm which exploits power saving opportunities at different levels of granularity simultaneously. Integrated with a performance-aware traffic allocation policy, Chameleon is able to achieve both high power efficiency and good performance at varying network utilization. Our experimental results show that Chameleon delivers an average of 3.39% higher performance than Catnap, the best in the literature. More importantly, Chameleon consumes an average of 17.16% less power than Catnap.
Keywords
"Resource management","Routing","Algorithm design and analysis","Optimization","Logic gates","Computers","Power demand"
Publisher
ieee
Conference_Titel
Computer Design (ICCD), 2015 33rd IEEE International Conference on
Type
conf
DOI
10.1109/ICCD.2015.7357138
Filename
7357138
Link To Document