A wirelessly powered system with charge recovery logic

In this paper, charge recovery logic is proposed as an alternative to traditional or near-threshold CMOS logic for high-performance systems where the power is wirelessly delivered, e.g. bio-implantable devices. This approach has two primary, complementary advantages in i) providing a wirelessly transmitted sine-wave as the power clock source to the charge recovery logic and ii) eliminating the AC/DC power stage required to provide a stable supply voltage needed in CMOS circuits. The paper presents solutions to the main obstacles of this method and shows simulation results of a simple logic load designed in Efficient Charge Recovery Logic (ECRL) as part of a wireless powered system. The designed wirelessly powered ECRL (coined WP-ECRL) system i) consumes 15.2 × less power than full-swing CMOS and ii) operates at higher frequencies than near-threshold CMOS. These comparative trends in power dissipation are for the computing circuit only, and do not include the bulky AC/DC stage that would be necessary for CMOS implementations. In terms of resilience, it is shown that logic functionality is preserved even when the coupling coefficient of the wireless link is decreased by 60% from the nominal value or when coils with very poor quality factor (down to Q = 0.1) are used.