DocumentCode :
3712396
Title :
Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime
Author :
Yuxin Bai;Yanwei Song;Mahdi Nazm Bojnordi;Alexander Shapiro;Engin Ipek;Eby. G. Friedman
Author_Institution :
Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA
fYear :
2015
Firstpage :
527
Lastpage :
534
Abstract :
Near-threshold computing (NTC) is an effective technique for improving the energy efficiency of a CMOS microprocessor, but suffers from a significant performance loss and an increased sensitivity to voltage noise. MOS current-mode logic (MCML), a differential logic family, maintains a low voltage swing and a constant current, making it inherently fast and low-noise. These traits make MCML a natural selection to implement an NTC processor; however, MCML suffers from a high static power regardless of the clock frequency or the level of switching activity, which would result in an inordinate energy consumption in a large scale IC. To address this challenge, this paper explores a single-core microarchitecture for MCML that takes advantage of C-slow retiming technique, and runs at a high frequency with low complexity to save energy. This design principle is opposite to the contemporary multicore design paradigm for static CMOS that relies on a large number of gates running in parallel at modest speeds. When compared to an eight-core static CMOS processor operating in the near-threshold regime, the proposed processor exhibits 3x higher performance, 2x lower energy, and 10 x lower voltage noise, while maintaining a similar level of power dissipation.
Keywords :
"CMOS integrated circuits","Logic gates","Threshold voltage","Delays","Transistors","Switching circuits","Libraries"
Publisher :
ieee
Conference_Titel :
Computer Design (ICCD), 2015 33rd IEEE International Conference on
Type :
conf
DOI :
10.1109/ICCD.2015.7357161
Filename :
7357161
Link To Document :
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