Improving memristor memory with sneak current sharing

Several memory vendors are pursuing different kinds of memory cells that can offer high density, non-volatility, high performance, and high endurance. There are several on-going efforts to architect main memory systems with these new NVMs that can compete with traditional DRAM systems. Each NVM has peculiarities that require new microarchitectures and protocols for memory access. In this work, we focus on memristor technology and the sneak currents inherent in memristor crossbar arrays. A read in state-of-the-art designs requires two consecutive reads; the first measures background sneak currents that can be factored out of the current measurement in the second read. This paper introduces a mechanism to reuse the background sneak current measurement for subsequent reads from the same column, thus introducing "open-column" semantics for memristor array access. We also examine a number of data mapping policies that allow the system to balance parallelism and locality. We conclude that on average, it is better to prioritize locality; our best design yields a 20% improvement in read latency and a 26% memory power reduction, relative to the state-of-the-art memristor baseline.