A scan chain optimization method for diagnosis

Scan chain structure consumes 10%~30% of die area, and most yield loss is caused by scan chain faults. This makes scan chain diagnosis be the key important method to ensure the high-quality products. The conventional scan chain diagnosis techniques usually conduct to a large range of suspect faulty flip flops. The failure analysis of those suspect faulty flip flops is time-consuming and costly. In this paper, we present a new scan chain construction method to reduce the range of suspect faulty flip flops. By constructing scan chains based on circuit logical structure, the proposed method can effectively improve the diagnosability of scan chains without any additional circuits. Moreover, by taking into consideration the physical location, the proposed method can decrease the negative effects of scan chains on the performance of designs. The proposed scan chain construction method can effectively handle a single scan chain fault as well as multiple scan chain faults. The experimental results show that the range of suspect faulty flip flops is reduced by 40%~90% on the most of ITC´99 benchmark circuits.