DocumentCode :
3712409
Title :
Non-enumerative correlation-aware path selection
Author :
Ahish Mysore Somashekar;Spyros Tragoudas;Rathish Jayabharathi
Author_Institution :
Department of Electrical and Computer Engineering, Southern Illinois University, Carbondale, IL 62901, USA
fYear :
2015
Firstpage :
629
Lastpage :
634
Abstract :
The path delay fault model is effective in detecting small delay defects. The proposed approach identifies the delay behavior of paths in various circuit instances without enumerating them. It selects critical paths through path implicit operations on a compact data structure potentially containing an exponential number of path candidates. The experimental analysis on some of the largest ISCAS-89 and ITC-99 benchmarks shows that the proposed approach is highly scalable and effective.
Keywords :
"Delays","Correlation","Logic gates","Integrated circuit modeling","Clocks","Monte Carlo methods"
Publisher :
ieee
Conference_Titel :
Computer Design (ICCD), 2015 33rd IEEE International Conference on
Type :
conf
DOI :
10.1109/ICCD.2015.7357174
Filename :
7357174
Link To Document :
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