Sensitivity of the thermal profile of bump-bonded 3D systems to inter-die bonding layer properties

In three-dimensional integrated circuits (3DICs) aggressive wafer-thinning can lead to large thermal gradients, including spikes in individual device temperatures. In this paper we have simulated the impact of the inter-die bonding layer on the transistor temperatures of a two-tier bump-bonded 3D system for various thicknesses of the top tier. A 100 μm × 100 μm area of active devices in the top tier dissipates power at 250 W/cm², creating a hotspot in the middle of a 2 mm × 2 mm chip that dissipates power at 100 W/cm2. We found that when the top die is 200 μm thick all tested configurations of inter-die bonding layer properties met the thermal budget of the system, which was specified to be a temperature rise of less than 50 °C. When the top die thickness was decreased to 10 μm we found that the thermal conductivity of the inter-die bonding layer needed to either be 2 μm or less in thickness, or have a thermal conductivity of 1 W/m·K or more to meet the same thermal budget for all tested combinations of the other parameters.