Thermal characterization and modeling of BEOL for 3D integration

Thermal design of 3D integration is one of most important issues for implementing this technology in applications. The lack of uniformity in micro-bump interconnection and high thermal resistance in BEOL (Back End of Line) in chips may limit the heat dissipation path for the cooling method. Firstly, in this study, through steady state measurement and FEM analysis of a F2F (Face to face) sample, which was made of an actual LSI, the thermal resistance of BEOL was derived and a 3D stacked FEM model in chip size was built for thermal design use. Secondly, the cooling performance of the thermal bumps for hotspots was compared with varying bump pitches in both the FEM analysis and measurement. Thermal bumps can lower the temperature of not only the area where they are placed but also areas surrounded by them. Moreover, it can be thought that partially dense thermal bumps for hotspots are not superior to uniformly dense ones in terms of controlling the maximum temperature in a chip. However, they provide almost the same performance in terms of decreasing the temperature differences in the chip.