Arbitrary shape multilayer interconnects EMC modelling and optimization

In very-large-scale-integration (VLSI), arbitrary structure of interconnections leads to unpredictable parasitic capacitance that generates EMC issues, i.e., parasitic noise, signal disorder, control failure, data asynchronous, etc. This paper investigates an EMC modelling and optimization method in calculating interconnect capacitance of VLSI interconnects based on the finite element method (FEM). Two- and three-dimensional interconnect models are simulated and the results of capacitance extraction are compared with experimental measurements, which proved the consistency and accuracy of FEM. Furthermore, optimizations of coupling capacitance are applied on multilayer interconnection structures by the non-dominated sorting genetic algorithm II (NSGA-II).