Simulation model based on JEDEC JS-001-2014 for circuit simulation of HBM ESD pulses on IC level

A 3rd order lumped element circuit for the simulation of the JEDEC JS-001-2014 HBM ESD pulse is proposed. The resulting current pulse is analytically computed with a state space model of the circuit. For the purpose of verification a computer algebra system is used, solving and checking the model if it generates a current pulse which fulfils the requirements. The values of the voltage pulse, resistor, inductor and capacitor can be changed dynamically, resulting in an instant check against the standard which is also visualised by a plot. Finally the results are compared against numerical simulation in SPICE.