Implementation and analysis of an area efficient low power SQ-CSA in MCML technique

Adders play a vital role in various applications that need fast arithmetic operations. Square root carry select adder is among the fast adders and also has the possibilities of modification. This paper presents the implementation of proposed Square root carry select adder using MCML technique which results in reduced area and power. Analysis is done on the basis of area and power. Simulations are performed in T-SPICE using 16nm CMOS technology parameters. The results have been compared with the regular Square root Carry Select Adder. Results concludes that proposed MCML Square root Carry Select Adder has less area and power in comparison to regular Square root Carry Select Adder.