Low power technique in domino logic circuit

High performance circuits demands domino logic design. A new technique for reducing the power consumption and increasing the speed without effecting noise margin is reviewed in this paper. In this technique threshold voltage of the keeper transistor is varied using body bias generator circuit. Three different body bias generator circuits are simulated, they are dynamic body bias generator, capacitive body bias generator and cross couple capacitive body bias generator circuit. Simulations are performed on tanner EDA tool at 180 nm and 65nm technology, for carry look ahead adder. The simulation results show that CBBG and CCCBBG have reduced power consumption and delay in comparison to other circuit techniques.