Impacts on the anti-ESD/ anti-LU immunities by the drain-side superjunction structure of HV/ LV nMOSFETs

Experimental comparisons between the reference pure sample and composite devices with a super-junction (SJ) structure in the drain-side of low-voltage and high-voltage MOSFETs are investigated in this paper. From testing results, the drain-side engineering of super-junction methodology has negative (positive) impacts on the anti-ESD capability in the LV nMOSFET (HV nLDMOS) devices. Then as a result, the layout type of nMOSFET-SJ (nLDMOS-SJ) has a lower (higher) It2 and Vh values. Eventually, it can be summarized that this drain-side SJ structure of MOSFET device is a bad (good) choice for the anti-ESD/ anti-LU robustness improvements for the LV (HV) process.