A low-inductance packaging layout for 1.2kV, 40A Full-SiC power module embedding split damping capacitors

A novel packaging layout of Full-SiC(Silicon Carbide) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Module with split damping capacitors embedding inside innovatively is proposed, which decrease stray inductance greatly. Since the stray inductance of the commutation loop caused by bonding wires and patterns on the substrate will result in a large voltage spike over the semiconductor device. The module with damping capacitors inside will decrease the stray inductance of the commutation loop significantly. The stray inductance extracted by commercial simulation software ANSYS Q3D Extractor electromagnetic FEA (Finite Element Analysis) tool show that a total self-inductance of the single commutation loop is 6.2nH. The LTspice simulation based on the synchronous buck circuit shows a 55V voltage spike over the semiconductor on the current rate 6717A/μs. In this paper, the current difference between two parallel branches is simulated by LTspice and a remarkable performance is observed. These results demonstrate the validity of the proposed packaging structure of a Full-SiC Module.